A Compact 30-GHz 18-dBm Power Amplifier for 5G Communication in 180-nm CMOS

Authors

  • R. Govindan Department of Electronics and Communications Engineering, Kattankulathur campus, Chengalpattu, India
  • K. Suganthi Department of Electronics and Communications Engineering, Kattankulathur campus, Chengalpattu, India

Keywords:

Analog pre-distortion, Power amplifier, Power added Efficiency, Frequency, 5G

Abstract

Currently, there is a large move towards 5G wireless technology beyond the existing, widely used 4G technology due to an increased use of smart devices, and multimedia content. 5G technology is expected to operate at high frequencies between 1 GHz to 100 GHz opening up a new horizon for spectrum constrained future wireless communications. Designing high efficiency power amplifiers for such high frequencies presents a new challenge. This project designs an efficient Stacked Power Amplifier (PA) for 5G. The power amplifier is implemented in 180nm technology using LT spice tool. The usage of a diode pre-distorter for analog pre- distortion is investigated for the stacked Power amplifier design. It is shown, that the linearity of the stacked PA is significantly improved compared to a bipolar transistor at almost no additional layout size. This paper presents design of a 30 GHz power amplifier for fifth- generation (5G) mobile communication in CMOS design. The stacked power amplifier consists of two different stages of architecture. With 5-V supply, the stacked power amplifier achieves a small-signal gain of 16 dB, saturated output power (Psat) of 18 dBm, and achieves the maximum power added efficiency of 34.79%. The amplifier has been designed in 180-nm CMOS.

Downloads

Published

2021-04-25

How to Cite

[1]
R. Govindan and K. Suganthi, “A Compact 30-GHz 18-dBm Power Amplifier for 5G Communication in 180-nm CMOS”, IJRAMT, vol. 2, no. 4, pp. 113–117, Apr. 2021.

Issue

Section

Articles