Design and Verification of Layer 3 of OSI Model

Authors

  • T. S. Sagara Gouda Department of Electronics and Communication Engineering, JSS Academy of Technical Education Bangalore, India
  • S. M. Usha Department of Electronics and Communication Engineering, JSS Academy of Technical Education Bangalore, India

Keywords:

Router, Data packets, Verilog, Xilinx ISE

Abstract

Directing is the way toward moving a bundle of information from source to goal and empowers messages to go starting with one PC then onto the next and in the end arrive at the objective machine. It is a bundle based convention. Switch drives the approaching parcel which originates from the info port to yield ports dependent on the location contained in the bundle. The switch has a one info port from which the parcel enters. It has three yield ports where the bundle is driven out. In this undertaking we are atomizing the elements of the Router by composing the code in VERILOG and recreating it in QUESTASIM. It is associated with at least two information lines from various systems (instead of a system switch, which interfaces information lines from one single system). This undertaking, basically underscores upon the Design and check of switch gadget, its high level engineering, and how different sub-modules of switch for example Register, FIFO, FSM and Synchronizer are orchestrated, and mimicked lastly associated with its top module.

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Published

13-07-2020

How to Cite

[1]
T. S. . Sagara Gouda and S. M. . Usha, “Design and Verification of Layer 3 of OSI Model”, IJRESM, vol. 3, no. 7, pp. 9–12, Jul. 2020.

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Articles